Semiconductor memory devices are generally categorized as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM) depending on a method of maintaining stored data.
A basic memory cell in an SRAM comprises a flip-flop circuit. SRAM is considered reliable for data storage. By comparison, a DRAM comprises a capacitor as a basic memory cell. Unfortunately, charges of capacitors gradually discharge by leakage current. Accordingly, DRAM must be recharged to preserve data stored in its cells. This recharging operation is referred to as a refresh. In a refresh operation, data stored in a cell is read and amplified, and then restored in the cell.
FIG. 1 is a block diagram of a conventional semiconductor device for performing a refresh operation. Referring to FIG. 1, the conventional semiconductor device for the refresh operation comprises a memory unit 100, a bank selector 120 and a refresh controller 130.
Conventionally, a memory unit 100 includes a memory cell array 102, a row decoder 104, a column decoder 106 and a sense amplifier 108. The memory cell array 102 contains memory cells which are arranged by a plurality of rows and columns. The row decoder 104 selects and activates a word line (a row address) of each of the memory cells. The column decoder 106 selects and activates a bit line (a column address) of each of the memory cells. The sense amplifier 108 then amplifies data (charges) of a cell (a capacitor). The data is transferred by a bit line and then restored in the cell, thereby performing a refresh operation. In most semiconductor memory devices, the memory cell array 102 is structured by a plurality of banks (as a matter of convenience, assume four banks). Each bank may have a row and column decoder.
To perform a refresh operation, the bank selector 120 selects one bank among a plurality of banks, thus enabling a row decoder of a selected bank and disabling other row decoders.
If a refresh command is received, the refresh controller 130 sequentially generates row addresses depending on a predetermined clock signal CLK and then inputs them to row decoders connected to each of the banks. The CLK signal may be activated or deactivated at the internal clock controller by a clock enable (CKE) signal. At this time, whether the refresh command is input is sensed by a combination of a chip selection signal /CS, a column address strobe signal /CAS, a row address strobe signal /RAS and a write enable signal /WE.
In a refresh operation for the conventional memory device above, if the refresh command is applied from an external device, a bank may perform the refresh operation to enable an applicable row decoder. In addition, in the refresh controller 130, a row address is sequentially generated according to the refresh command and input to the row decoder. Only word line equivalent to an enabled row decoder becomes sequentially activated by the row address from the refresh controller 130.
If an activated word line is recharged to a certain electric potential, data from all cells connected to the word line is transferred through the bit line to the sense amplifier 108. The sense amplifier 108 may therefore amplify the data and restore it in the original cell(s). As a result, the refresh operation is performed.
A recent data storage method improves the operation speed of semiconductor memories. According to the method, data is stored at a block unit instead of a bank unit. That is, each bank is divided into a plurality of blocks, and data is dispersed and stored in each of the blocks. This happens because as data is stored or read, changing a word line about one bank is still faster than activating a bank.